The Super-H is a series of
processors developed by Hitachi, and is now distributed by
Renesas. The Super-H is probably best known for the sega consoles 32x (SH-2) Saturn (SH-2) and Dreamcast (SH-4), it was also used in some Pocket PCs The Super-H is also known as the SH7600 series (SH-2) and SH7700 series (SH-3) There is also an open source implementation of the SH-2, known as the J-core We'll only be covering the SH-2 in these tutorials, and we'll use the 32X emulator for our testing! |
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If you want to learn SH2 get the Cheatsheet! it has all the Super-H commands, It will help you get started with ASM programming, and let you quickly look up commands when you get confused! | ![]() |
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We'll
be
using ASW as our assembler for these tutorials You can get the source and documentation for ASW from the official website HERE |
General Purpose Registers:
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Special Registers:
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MACH was only 10 bit on the SH-1 CPU (SH7000)
MACH is fully 32 bit on the SH-2 CPU (SH7600)
F |
E |
D |
C |
B |
A |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
F |
E |
D |
C |
B |
A |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
M |
Q |
I |
I |
I |
I |
- |
- |
S |
T |
T= Carry Bit
S = Used by Multiply and Accumulate
I = Interrupt mask bits
M and Q
= used by Div
The Super-H can run
in Big or Little endian mode! On the 32X it runs in Big Endian, like the 68000 |
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Mode | Format | Notes | Example |
Direct register addressing | Rn | The effective address is register Rn. (The operand is the contents of register Rn.) | |
Indirect register addressing | @Rn | The effective address is the content of register Rn | |
Post-increment indirect register addressing | @Rn+ | The effective address is the content of register Rn. Rn is incremented by the amount loaded (B/W/L = 1/2/4) |
|
Pre-decrement indirect register addressing | @–Rn | First, Rn is decremented by the amount loaded (B/W/L = 1/2/4) The effective address is the value obtained by subtracting a constant from Rn. |
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Indirect register addressing with displacement | @(disp:4,Rn) | The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zero- extended, and remains the same for a byte operation, is doubled for a word operation, or is quadrupled for a longword operation. | |
Indirect indexed register addressing | @(R0, Rn) | The effective address is the Rn value plus R0 (RN+R0) | |
Indirect GBR addressing with displacement | @(disp:8,GBR) | The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, or is quadrupled for a longword operation. | |
Indirect indexed GBR addressing | @(R0,GBR) | The effective address is the GBR value plus R0. (GBR + R0) | |
PC relative addressing with displacement |
@(disp:8,PC) | The effective address is the PC value plus an 8-bit displacement
(disp). The value of disp is zero- extended, and disp is doubled for a word operation, or is quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC are masked. |
|
PC relative addressing (8 bit) | disp:8 | The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC. (PC + disp * 2) | |
PC relative addressing (8 bit) | disp:12 | The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC. (PC + disp * 2) | |
PC relative addressing (Register) | Rn | The effective address is the register PC plus Rn. (PC + Rn) | |
Immediate addressing | #imm:8 | Immediate is zero extended for TST,AND,OR and XOR Immediate is sign extended for MOV, ADD and CMP/EQ Immediate is zero extended and quadrupled for TRAPA |
Branch Delay Slots
JMP, BRA, JSR, BSR, BSRF, RTE and RTS all have a delay slot after them, meaning the command after these instructions will occur before the jump!... if that sounds annoying (Which it is!) just put a NOP after these commands!
BF/S and BT/S also have a delay slot... that's what the /S means!
BF and BT do not have a delay slot.
There are also no load delays on the Super-H.