SH2 Assembly programming for
the 32x
The 32x was an upgrade to the
Genesis. Plugging onto the Genesis, and overlaying it's video via
connecting video cables. it's a rather odd, but 'somewhat' effective
solution to upgrading the Genesis. Unfortunately consumer
confusion (and the upcoming saturn) left the 32x dead in the water,
and it was a commercial failure.
While graphically capable, and with some sound functions, it also
uses the Genesis for it's music chip, and joypad access (VIA a
separate 68000 program)... many games also used the Genesis VDP for
some graphics!
In fact, execution starts on the 68000 side, so it is impossible to
have a SH2 only 32x cartridge.
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Cpu |
Dual SH2 (23mhz) |
Ram |
256K Ram |
Video |
256k Vram |
Resolution |
320x240 |
Sound |
PCM + Genesis sound |
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Genesis 68000 Memory Map
The 32x add on changes the Genesis memory map:
Address
|
Purprose |
$000000 |
Vector Rom |
$400000 |
Same as Megadrive |
$840000 |
Frame buffer |
$860000 |
Overwrite Image |
$880000 |
Rom Cartridge |
$900000 |
Rom Cartridge (4 bank swtch) |
$A00000 |
Same as Megadrive |
$A130EC |
Super32x ID |
$A130F0 |
Same as Megadrive |
$A15100 |
Super32x Sys Reg |
$A15180 |
VDP Regs |
$A15200 |
Color Palette |
$A15400 |
Same as Megadrive |
Genesis 68000 Hardware Registers
Address
|
Purpose |
Bits
|
Details |
$A5100 |
Adapter Control Register |
%F-------R-----rA |
F=VDP Access Auth (1=sh2 0=md) R=Sh2 Reset enable
r=reset(0=reset) A=Adapter enable (1=32x on) |
$A5102 |
Interrupt control register |
%--------------SM |
S=Slave sh2 interrupt M=Master SH2 interrupt |
$A5104 |
Bank Set Register |
%--------------BB |
Bank in $900000-$9FFFFF |
$A5106 |
DREQ control register |
%--------F----S0R |
F=1=Full R=1=rom to vram start |
$A5108 |
DREQ Source Reg H |
%--------HHHHHHHH |
|
$A510A |
DREQ Source Reg L |
%LLLLLLLLLLLLLLL0 |
|
$A510C |
DREQ Dest Reg H |
%--------HHHHHHHH |
|
$A510E |
DREQ Dest Reg L |
%LLLLLLLLLLLLLLL0 |
|
$A5110 |
DREQ Length |
%LLLLLLLLLLLLLL00 |
No of words to transfer |
$A5112 |
FIFO Reg |
%???????????????? |
|
$A511A |
Sega TV Register |
%---------------C |
C=0=Rom 1=Dram |
$A5120 |
2way Coms with SH2 |
|
($20004020 on SH2) |
$A5122 |
2way Coms with SH2 |
|
($20004022 on SH2) |
$A5124 |
2way Coms with SH2 |
|
($20004024 on SH2) |
$A5126 |
2way Coms with SH2 |
|
($20004026 on SH2) |
$A5128 |
2way Coms with SH2 |
|
($20004028 on SH2) |
$A512A |
2way Coms with SH2 |
|
($2000402A on SH2) |
$A512C |
2way Coms with SH2 |
|
($2000402C on SH2) |
$A512E |
2way Coms with SH2 |
|
($2000402E on SH2) |
$A5130 |
PWM Sound Source Control Reg |
%----TTTTR---rrLL |
T=Timer interrupt interval R=Dreq1 occurrence enable
lr=L/R |
$A5132 |
Cycle Register |
%----CCCCCCCCCCCC |
Cycle counter |
$A5134 |
L ch pulse width |
%FE--DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5136 |
R ch pulse width |
%FE--DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5138 |
mono pulse width |
%FE--DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5180 |
Bitmap Mode Register |
%P-------pL----MM |
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32X SH2 Memory Map
Here is the Memory map as seen by the SH2
Cache Through
Address
|
Cache
Address
|
Purpose |
$20000000 |
$00000000 |
Boot Rom |
$20004000 |
$00004000 |
Super 32x Sys Reg |
$20004100 |
$00004100 |
VDP Reg |
$20004200 |
$00004200 |
Color Palette |
$20004400 |
$00004400 |
- |
$22000000 |
$02000000 |
Rom Cartridge |
$22400000 |
$02400000 |
- |
$24000000 |
$04000000 |
Frame Buffer (Vram) |
$24020000 |
$04020000 |
Overwrite Image |
$24040000 |
$04040000 |
- |
$26000000 |
$06000000 |
SDRAM |
$26040000 |
$06040000 |
- |
$28000000 |
$08000000 |
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32X SH2 Hardware Registers
68000 Equivalent |
SH2 Cache
Through Address |
Purpose |
Bits |
Details |
|
$20040000 |
Interrupt mask |
%F-----ACH---VHCP |
F=Vdp access (0=MD 1=SH2) A=Adapter enable (1=32x on)
C=Cart in?(1=no) H=H-int(1=on) C=Command int on P=PWM timer
interrupt |
|
$20040002 |
Stand by change register |
Used by System Boot Rom only |
|
|
$20040004 |
Hcount Register |
%--------HHHHHHHH |
H=Hint occurrence |
$A5106 |
$20040006 |
DREQ Control register |
%FE-----------S0R |
F=1=Full E=1=Empty |
$A5108 |
$20040008 |
DREQ Source Reg H |
%--------HHHHHHHH |
|
$A510A |
$2004000A |
DREQ Source Reg L |
%LLLLLLLLLLLLLLL0 |
|
$A510C |
$2004000C |
DREQ Dest Reg H |
%--------HHHHHHHH |
|
$A510E |
$2004000E |
DREQ Dest Reg L |
%LLLLLLLLLLLLLLL0 |
|
$A5110 |
$20040010 |
DREQ Length |
%LLLLLLLLLLLLLL00 |
No of words to transfer |
$A5112 |
$20040012 |
FIFO Reg |
%???????????????? |
|
|
$20004014 |
Vres interrupt clear |
|
|
|
$20004016 |
V interrupt clear |
|
|
|
$20004018 |
H interrupt clear |
|
|
|
$2000401A |
Cmd interrupt clear |
|
|
|
$2000401C |
Pwm interrupt clear |
|
|
$A5120 |
$20040020 |
2way Coms with SH2 |
($A5120 on 68000) |
|
$A5122 |
$20040022 |
2way Coms with SH2 |
($A5122 on 68000) |
|
$A5124 |
$20040024 |
2way Coms with SH2 |
($A5124 on 68000) |
|
$A5126 |
$20040026 |
2way Coms with SH2 |
($A5126 on 68000) |
|
$A5128 |
$20040028 |
2way Coms with SH2 |
($A5128 on 68000) |
|
$A512A |
$2004002A |
2way Coms with SH2 |
($A512A on 68000) |
|
$A512C |
$2004002C |
2way Coms with SH2 |
($A512C on 68000) |
|
$A512E |
$2004002E |
2way Coms with SH2 |
($A512E on 68000) |
|
$A5130 |
$20040030 |
PWM Sound Source Control Reg |
%----TTTTR---rrLL |
T=Timer interrupt interval R=Dreq1 occurrence enable
lr=L/R |
$A5132 |
$20040032 |
Cycle Register |
%----CCCCCCCCCCCC |
Cycle counter |
$A5134 |
$20040034 |
L ch pulse width |
%FE�DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5136 |
$20040036 |
R ch pulse width |
%FE�DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5138 |
$20040038 |
mono pulse width |
%FE�DDDDDDDDDDDD |
FE=Full/Empty (read) D=Data (Write) |
$A5180 |
$20040100 |
Bitmap Mode Register |
%P-------pL----MM |
P=Pal/Ntcs p+priority(1=32x) L=240 line? M=screen
mode (pixel format) |
$A5182 |
$20040102 |
Screen Shift Control |
%---------------S |
S=Shift 1 dot |
$A5184 |
$20040104 |
Auto Fill Length |
^--------LLLLLLLL |
Length to fill in words |
$A5186 |
$20040106 |
Auto Fill Start Address |
%AAAAAAAAAAAAAAAA |
A=Address |
$A518A |
$2004010D |
Auto Fill Data |
%DDDDDDDDDDDDDDDD |
D=Data to fill |
$A518A |
$2004010A |
Frame Buffer control reg |
%VHP-----------FS |
V=Vblank H=Hblank P=Palette accessable F=frame buffer
accessible S=Swap vram to VDP |
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Buy my Assembly programming book on Amazon in Print or Kindle!
Available worldwide! Search 'ChibiAkumas' on your local Amazon website!
Click here for more info!
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