Learn Multi platform PowerPC Assembly Programming... And feel the POWER!

The PowerPC processor is IBM's Desktop CPU comparable to the Intel x86 CPUs. Based on the previous POWER workstation CPUs, its RISC instruction set gave impressive speed and capabilities.

PowerPC became extremely popular around 2000, and was the basis for the Power Mac series, Gamecube, WII, Xbox360 and (to some extent) the PS3





If you want to learn POWERPC get the Cheatsheet! it has all the PowerPC commands, It will help you get started with ASM programming, and let you quickly look up commands when you get confused!

We'll be using ASW as our assembler for these tutorials
You can get the source and documentation for ASW from the official website HERE



The PowerPC Registers
All PowerPC registers are fully 32 bit.
There are 32 general purpose registers, and a few which have special purposes, and limited commands which can access their values

General Purpose Registers:
R0
General Purpose
R1 / SP
Used as Stack Pointer
R2 / RTOC
Table Of Contents pointer
R3 General Purpose - Arg1
R4 General Purpose - Arg2
R5 General Purpose - Arg3
R6 General Purpose - Arg4
R7 General Purpose - Arg5
R8 General Purpose - Arg6
R9 General Purpose - Arg7
R10 General Purpose - Arg8
R11 General Purpose
R12 General Purpose
R13 Reserved on 64 bit (free on 32 bit)
R14 General Purpose - NonVolatile
R15
General Purpose - NonVolatile
R16
General Purpose - NonVolatile
R17
General Purpose - NonVolatile
R18
General Purpose - NonVolatile
R19
General Purpose - NonVolatile
R20
General Purpose - NonVolatile
R21
General Purpose - NonVolatile
R22
General Purpose - NonVolatile
R23
General Purpose - NonVolatile
R24
General Purpose - NonVolatile
R25
General Purpose - NonVolatile
R26
General Purpose - NonVolatile
R27
General Purpose - NonVolatile
R28
General Purpose - NonVolatile
R29
General Purpose - NonVolatile
R30
General Purpose - NonVolatile
R31
General Purpose - NonVolatile
Floating Point Registers:
F0
General Purpose - Scratch reg
F1
General Purpose - Arg1
F2
General Purpose - Arg2
F3 General Purpose - Arg3
F4 General Purpose - Arg4
F5 General Purpose - Arg5
F6 General Purpose - Arg6
F7 General Purpose - Arg7
F8 General Purpose - Arg8
F9 General Purpose - Arg9
F10 General Purpose - Arg10
F11 General Purpose - Arg11
F12 General Purpose - Arg12
F13 General Purpose - Arg13
F14 General Purpose - NonVolatile
F15
General Purpose - NonVolatile
F16
General Purpose - NonVolatile
F17
General Purpose - NonVolatile
F18
General Purpose - NonVolatile
F19
General Purpose - NonVolatile
F20
General Purpose - NonVolatile
F21
General Purpose - NonVolatile
F22
General Purpose - NonVolatile
F23
General Purpose - NonVolatile
F24
General Purpose - NonVolatile
F25
General Purpose - NonVolatile
F26
General Purpose - NonVolatile
F27
General Purpose - NonVolatile
F28
General Purpose - NonVolatile
F29
General Purpose - NonVolatile
F30
General Purpose - NonVolatile
F31
General Purpose - NonVolatile
Special Registers:
LR
Link Register (Return Address)
CTR
CounT Register (for loop counts)
XER
eXcEption Register
FPSCR
Floating Point exception Register
CR
Condition register

Note:
There is no accessible PC register

The value in NonVolatile registers must be preserved by subs

R3-R10 are suggested for passing arguments to a sub

R0 is used as a temp register during the 'Prolog/Epilog' of a sub (the Init and Cleanup of the stack during a sub

Condition Register
The 32 bit condition register is split into 8x 4 bit parts.

Bits
31.28
27.24
23.20
19.16
15.12
11..8
7...4
3...0
Purpose
CR7
CR6
CR5
CR4
CR3
CR2
CR1 CR0

CR2, CR3 and CR4, are Non Volatile, and must be preserved by subs

Each of the 4 CR bits for CR0-CR7 have the following purpose:
Bit
3
2
1
0
Meaning
Summary
Overflow
(SO)
Zero
(EQ)
Positive
(GT)
Negative
(LT)


The PowerPC is typically a BIG Endian system, certainly in the case of the GameCube/WII, and apparently the Xbox 360

Though in fact the PowerPC can function in Little Endian mode

Addressing Modes
Mode Format Notes Example
Signed Immediate SIMM 16 bit signed Immediate addi rD,rA,SIMM
Unsigned Immediate UIMM 16 bit unsigned Immediate cmplwi crfD,rA,UIMM
Register rD,Ra,RB Leftmost param is destination (rD) add rD,rA,rB
Indirect with offset d(rA) Dest Address= value in rA + 16 bit signed immediate d stbu rS,d(rA)
Unconditional Address imm_addr 24 bit signed address b imm_addr
Conditional Address target_addr 14 bit signed address blt target
bc 12,O,target