	
	org $06000000

;Cpu 2 Entry
	
Cpu2Loop:
	bra	Cpu2Loop;$06000000
	nop	;(Delay slot?)
	
;Cpu 1 Entry
	mov.l Cpu1_ProgStartAddr,r0	;6000010
	jsr	@r0		;Start CPU1 program
	nop		;(Delay slot?)
	nop	
	
Cpu1_ProgStartAddr:
	dc.l Cpu1_ProgStart
	
Cpu1_ProgStart:	
	
	mov.l #UserRam,r14		;R14 points to our work ram
	mov.l #$20004000,r2		;20004000 -32x Registers (64 bytes) - MIRROR
		
Waitfor68k:
	mov.w	@r2,r1			;MSH2_WW_IntC		Bus Controller
	exts.w	r1,r1
	cmp/pz	r1				;Bit 15=1 means SH2 has VDP
	bt	Waitfor68k
	
	mov.l #$20004100,r1		;20004100 - VDP Registers (16 bytes) - MIRROR
	mov	#1,r2
	mov.w	r2,@r1			;Packed pixel Mode (8bpp palette)
	
	
	mov.l #$20004200,r6		;20004200 - VDP CRAM (512 bytes)	 - MIRROR
	
	mov.l #Palette,r8		;Palette
	mov	#4,r0				;PaletteEntries
	
PaletteLoop:
	mov.w @r8+,r1
	mov.w r1,@r6
	add	#2,r6
	
	dt r0
	bf PaletteLoop 
	
	
	mov #DoLineTable,r13
	jsr @r13			;Define Line table 1
	nop
	
	mov #PageFlip,r13
	jsr @r13			;Flip Buffer
	nop
	
	mov #DoLineTable,r13
	jsr @r13			;Define Line table 2
	nop
	
	
	mov #0,r0
	mov.l r0,@(UserRam_CursorX,r14)
	mov.l r0,@(UserRam_CursorY,r14)

	bra ProgramStart
	nop
	
	align 4
	ltorg
	
	align 4	
ProgramStart: