	include "\SrcAll_SH2\BasicMacros.asm"
	include "\SrcAll_SH2\BasicHeader.asm"
	




	
	;bra ImmediateDirect
	;nop
	
	;bra Indirect
	;nop
	
	;bra IncrementDecrement
	;nop
	
	;bra IndirectIndex
	;nop

	;bra ProgramCounter
	;nop

	;bra PCRelative
	;nop
	
	bra GlobalBaseRegister
	nop
	
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
		
;#imm:8 	Immediate addressing
;			Immediate is zero extended for TST,AND,OR and XOR
;			Immediate is sign extended for MOV, ADD and CMP/EQ
;			Immediate is zero extended and quadrupled for TRAPA

ImmediateDirect:
	mov #-100,r0		;-128 to +127
	mov #1,r1			;-128 to +127
	mov #100,r2			;-128 to +127
		
	bsr Monitor3		;Show R0,R1,R2
	nop					;Must Put a NOP after BSR (Delay slot)
	
		
	and #%11110000,r0	;Logical ops do not sign extend (R0 only)
	;and #%11110000,r1	;This won't work (R0 only)
			
	bsr Monitor3
	nop					;Must Put a NOP after BSR (Delay slot)
		
	bsr NewLine
	nop
	
		
;Rn			Direct register addressing	
;			The effective address is register Rn. 
;			(The operand is the contents of register Rn.)

	bsr Monitor3		;Show R0,R1,R2
	nop					;Must Put a NOP after BSR (Delay slot)

	mov r0,r1
	
	bsr Monitor3		;Show R0,R1,R2
	nop					;Must Put a NOP after BSR (Delay slot)
	
	mov r2,r0
	
	bsr Monitor3		;Show R0,R1,R2
	nop					;Must Put a NOP after BSR (Delay slot)
	
	bra ExampleDone
	nop
	
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
	
;@Rn		Indirect register addressing
;			The effective address is the content of register Rn

Indirect:
	mov #TestAddr,r5
	mov #TestAddr+4,r4
	mov #$FFEEDDCC,r3
	
	mov.l @r5,r0	;Move 32 bit from the address in R5 to R0
	mov.w @r5,r1	;Move 16 bit from the address in R5 to R1
	mov.b @r5,r2	;Move 8 bit from the address in R5 to R2
	
	bsr Monitor3		;Show R0,R1,R2
	nop					;Must Put a NOP after BSR (Delay slot)
	
	mov #16,r2			;Bytecount
	mov #TestAddr,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop
	
	mov r3,@r4			;Store 32 bit value in R3 to address in R4
	
	mov #16,r2			;Bytecount
	mov #TestAddr,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop
			
	bra ExampleDone
	nop
			
	ltorg		;Literal Org, Values too large will be 
					;stored here by the assembler 
TestAddr:	dc.l $12345678
			dc.l $FFFFFFFF
			dc.l $11121314
			dc.l $21222324
	
	align 4		;Ensure we're still 32 bit aligned (4 bytes = 32 bit)
	
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;disp:12 				PC relative addressing (12 bit)
;						The effective address is the PC value sign-extended
;						 with a 12-bit displacement (disp), doubled, and
;						 added to the PC. (PC + disp * 2)
	
PCRelative:
	mov #'A',r0			;Load R0 with 'A'
	bsr PrintChar		;Branch to subroutine Printchar
	nop
	
	bsr ShowB			;Calculated as BSR 30 (12 bit offset)
	nop
	
	bra SkipC			;Calculated as BRA 8 (12 bit offset)
	nop
	
	mov #'C',r0
	bsr PrintChar
	nop	
SkipC:

;disp:8					PC relative addressing (8 bit)
;						The effective address is the PC value sign-extended
;						 with an 8-bit displacement (disp), doubled, and
;						 added to the PC. (PC + disp * 2)

	;mov #0,r0
	mov #1,r0
	cmp/eq #0,r0		;R0=0 ?

	bt SkipD			;calculated as BT 6 (8 bit offset)
	
	mov #'D',r0
	bsr PrintChar
	nop

;Rn						PC relative addressing (Register)
						;The effective address is the register
						; PC plus Rn. (PC + Rn)	
	;bsrf r0
		
SkipD:	
	bra ExampleDone
	nop
	
ShowB:
	sts.l pr,@-sp		;Back up PR (used by BSR/RTS)
		mov #'B',r0
		bsr PrintChar
		nop
	lds.l @sp+,pr		;Restore PR (used by BSR/RTS)	
	rts	
	nop
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
;@(disp:8,GBR)			Indirect GBR addressing with displacement
						;The effective address is the GBR value plus an 
						; 8-bit displacement (disp). The value of disp is
						; zero-extended, and remains the same for a byte
						; operation, is doubled for a word operation, or 
						; is quadrupled for a longword operation.

GlobalBaseRegister:
	mov #TestAddr4,r5
	ldc r5,gbr			;Transfer R0 to the GBR register

	mov.l @(8,gbr),r0	;Load from address GBR+4 to R0
		
	mov.l r0,@(0,gbr)	;Save R0 to address GBR+8
	
	;mov.l (4,gbr),r1	;Doesn't work! Source / Destination must be R0
	
;@(R0,GBR)				Indirect indexed GBR addressing
;						The effective address is the GBR value plus R0. 
; 					 	 (GBR + R0) - Logical Ops only!

	bsr Monitor			;Show Registers
	nop			
	
	mov #4,r0
	and.b #$0F,@(r0,gbr)	;And address GBR+R0 with 1
	;mov.l r0,@(r0,gbr)		;Doesn't work! Logical ops only!
		
	
	mov #16,r2			;Bytecount
	mov #TestAddr4,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop		
			
	bra ExampleDone
	nop
			
TestAddr4:	dc.l $11121314
			dc.l $21222324
			dc.l $31323334
			dc.l $41424344	
		
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	


;@Rn+		Post-increment indirect register addressing
;			The effective address is the content of register Rn.
;			Rn is incremented by the amount loaded (B/W/L = 1/2/4)

IncrementDecrement:	
	mov #16,r2			;Bytecount
	mov #TestAddr,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop
	
	bsr NewLine
	nop
		
	mov #TestAddr5,r5
	
	mov @r5+,r0			;Load a 32 bit Word and inc
	mov.l @r5+,r1		;Load a 32 bit Long and inc
	mov.w @r5+,r2		;Load a 16 bit Word and inc
	mov.b @r5+,r3		;Load a 8 bit Byte and inc

	bsr Monitor6		;Show Registers
	nop					

;@–Rn 		Pre-decrement indirect register addressing
;			First, Rn is decremented by the amount loaded (B/W/L = 1/2/4)
;			The effective address is the value obtained by subtracting a constant from Rn.

	mov #1,r0
	mov #-2,r1
	mov #3,r2
	mov #-4,r3
	
	mov #TestAddr+16,r5		;Need to be word aligned for 16/32 bit
	;mov #TestAddr+15,r5		;Not Word aligned, this will be weird!
	
	mov r0,@-r5				;Store 1		(32 bit)
	mov.l r1,@-r5			;Store -2 ($FE)	(32 bit)
	mov.w r2,@-r5			;Store 3		(16 bit)
	mov.b r3,@-r5			;Store -4 (FC)	(8 bit)
	
	bsr Monitor6		;Show Registers
	nop		
	
	mov #16,r2			;Bytecount
	mov #TestAddr,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop
	
	bsr NewLine
	nop
	
	bsr NewLine
	nop
	
;These commands are used with the stack,
; to back up and restore values

	bsr Monitor3		;Show Registers
	nop			

	mov r0,@-sp			;Back up R0
	mov r1,@-sp			;Back up R1
	mov r2,@-sp			;Back up R2
	
		mov #1,r0
		mov #2,r1
		mov #3,r2
		
		bsr Monitor3		;Show Registers
		nop		
		
	mov @sp+,r2			;Restore R2
	mov @sp+,r1			;Restore R1
	mov @sp+,r0			;Restore R0
		
	bsr Monitor3		;Show Registers
	nop		
		
	bra ExampleDone
	nop
			
	ltorg		;Literal Org

TestAddr5:	dc.l $12345678
			dc.l $FFFFFFFF
			dc.l $11121314
			dc.l $21222324
	
	align 4		;Ensure we're still 32 bit aligned (4 bytes = 32 bit)
	
		
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
	


;@(disp:4,Rn) 	Indirect register addressing with displacement
;				The effective address is Rn plus a 4-bit displacement (disp). 
;				The value of disp is zero- extended, and remains the same 
;				 for a byte operation, is doubled for a word operation,
;				 or is quadrupled for a longword operation.

IndirectIndex:
	mov #TestAddr2,r5

	mov @(0,r5),r1			;Load 32 bit long R1 from address in R5+0
	mov.l @(4,r5),r2		;Load 32 bit long R2 from address in R5+4
	
MyFaveVal equ 8				;Symbols are useful as offsets!
	mov.l @(MyFaveVal,r5),r3 ;Load 32 bit long R2 from address in R5+MyFaveVal
	
	mov r5,@(12,r5)			;Can also be used for saving values
		
	;mov @(-4,r5),r0		;Offset can't be negative!
	;mov.w @(4,r5),r2		;This won't work, Dest must be R0
	;mov.b @(5,r5),r3		;This won't work, Dest must be R0
		
	bsr Monitor6			;Show Registers
	nop		
	
	mov.w @(4,r5),r0		;Load 16 bit Word R0 from address in R5+0
	mov r0,r1
	
	mov.b @(5,r5),r0		;Load 8 bit Byte R0 from address in R5+0
		
	bsr Monitor6			;Show Registers
	nop		
	
	mov #16,r2				;Bytecount
	mov #TestAddr2,r1		;SourceAddr
	bsr MemDump				;Show Memory
	nop
	
	bsr NewLine
	nop
	bsr NewLine
	nop
	
;@(R0, Rn)		Indirect indexed register addressing
;				The effective address is the Rn value plus R0 (RN+R0)

	mov #0,r0
	
	mov.l @(r0,r5),r1		;Load 32 bit long R1 from address in R5+R0
	
	add #4,r0
	mov.w @(r0,r5),r2		;Load 16 bit word R2 from address in R5+R0
	
	add #4,r0
	mov.b @(r0,r5),r3		;Load 16 bit word R2 from address in R5+R0
	
	;mov.w @(r1,r5),r2		;index register must be R0
	
	add #4,r0
	mov r0,@(r0,r5)			;Can also be used for saving values
			
	bsr Monitor6			;Show Registers
	nop			
	
	mov #16,r2				;Bytecount
	mov #TestAddr2,r1		;SourceAddr
	bsr MemDump				;Show Memory
	nop		
		

		
	bra ExampleDone
	nop
		
	
	
TestAddr2:	dc.l $11121314
			dc.l $21222324
			dc.l $31323334
			dc.l $41424344	
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
	
;@(disp:8,PC) 	PC relative addressing with displacement
;				The effective address is the PC value plus 
;				 an 8-bit displacement (disp). The value of disp is zero-
;				 extended, and disp is doubled for a word operation, or is
;				 quadrupled for a longword operation. For a longword
;				 operation, the lowest two bits of the PC are masked.
	
ProgramCounter:

	mov.l @(4,pc),r1		;PC points to current command +4
							;we load  from PC+4
							
	bsr SkipData			;2 bytes
	nop						;2 Bytes	<-PC Points here 
	nop						;2 bytes
		
		dc.l $FFEEDDCC		;PC+4 is here
		align 4
SkipData:			
	
	mov #TestAddr3,r0		;this asssmbles to "mov.l @(??,pc),r0"
	
	bsr Monitor6			;Show Registers
	nop					
	
	mov #16,r2			;Bytecount
	mov #TestAddr3,r1	;SourceAddr
	bsr MemDump			;Show Memory
	nop		
	
	bsr NewLine
	nop
	bsr NewLine
	nop
	
;Effective Address

	mova @(4,pc),r0 	;R0=PC+4... PC = currentline+4 
	
	;mova @(2,pc),r0 	;Won't work... must be a multiple of 4
	;mova @(4,pc),r1 	;Won't work... destination must be R0
	
	bsr Monitor			;Show Registers
	nop			
				
	bra ExampleDone
	nop
	
	align 4
	
	LTORG				;Long immediates will actually be stored here
	
TestAddr3:	dc.l $11121314
			dc.l $21222324
			dc.l $31323334
			dc.l $41424344	

	align 4	

	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
		
ExampleDone:	
	bsr PageFlip			;Flip Buffer (for 32x)
	nop
	
InfLoop:	
	bra	InfLoop
	nop

;Anything too big for a 16 bit command (EG #$12345678) will be put
; at LTORG automatically by our assembler!
	
	ltorg		;Literal Org, Values too large will be stored here by the assembler 
		
	align 4		;Ensure we're still 32 bit aligned (4 bytes = 32 bit)
	

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
	


Monitor3:
	pushall
		mov sp,r3
		add #60,r3	;Point to first pushed reg
		mov #0,r1 	;Reg label
		
		mov #3,r5	;Reg per line
		
		mov #3,r4	;Reg count
MonitorAgain3:
		mov.l @r3,r2	;Get reg
		add #-4,r3		;Move to next reg
		
		bsr ShowReg
		nop
				
		add #1,r1		;Reg label
		
		dt r5
		bf MonitorNoNL3
		
		mov #3,r5	;Reg per line
		bsr NewLine
		nop
MonitorNoNL3:
		dt r4
		bf MonitorAgain3
		
		bsr NewLine
		nop
	popall
	rts
	nop
	
Monitor6:
	pushall
		mov sp,r3
		add #60,r3	;Point to first pushed reg
		mov #0,r1 	;Reg label
		
		mov #3,r5	;Reg per line
		
		mov #6,r4	;Reg count
MonitorAgain6:
		mov.l @r3,r2	;Get reg
		add #-4,r3		;Move to next reg
		
		bsr ShowReg
		nop
				
		add #1,r1		;Reg label
		
		dt r5
		bf MonitorNoNL6
		
		mov #3,r5	;Reg per line
		bsr NewLine
		nop
MonitorNoNL6:
		dt r4
		bf MonitorAgain6
		
		bsr NewLine
		nop
	popall
	rts
	nop
		
	include "\SrcAll_SH2\BasicFooter.asm"
	
	